Skip to content

中文版

Last Updated: 2025/5/3

Jingbo Gao (高靖博)

Email: gaojingbo0620 at outlook dot com

About Me

  • AI processor core designer
  • Familiar with computer Arch/µArch, RTL design, formal datapath verification, Verilog/SystemVerilog, and Scripts (Python, Bash, Tcsh, etc.)

Experience

  • Senior RTL Design Engineer, Alibaba T-Head Semiconductor, Apr 2025 - Present
  • RTL Design Engineer, Alibaba T-Head Semiconductor, Jul 2022 - Apr 2025
  • RTL Design Intern, Alibaba T-Head Semiconductor, Jun 2021 - Sep 2021

Education

  • MS, Microelectronics and Solid State Electronics (IC Design), Fudan University, 2019 - 2022
    • Grade: 3.8 out of 4.0 (Rank 1 out of 47)
    • Designed and implemented server-grade NPUs (Neural Processing Units)
    • Published a research paper on optimized NPU architecture for lightweight CNN models
    • Thesis: FPGA-Based Reconfigurable Accelerator for EfficientNets
  • UG Exchange Program, Hong Kong University of Science and Technology, 2018
    • Grade: 4.0 out of 4.3
    • Courses Taken
      • Computer Organization
      • Computer Communication Network
      • Digital VLSI System Design and Design Automation (for PhD/MPhil)
      • IC Fabrication Technology
      • Machine Learning
  • BE, Microelectronic Science and Engineering, Fudan University, 2015 - 2019
    • Grade: 3.5 out of 4.0
    • Shanghai Outstanding Graduate Award (Top 5%)
    • Published a research paper on TCP/IP offload engine architecture for latency sensitive applications
    • Thesis: Design and Implementation of TCP Offload Engine

Selected Publications (Full-List)

  1. Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang, "LETA: A lightweight exchangeable-track accelerator for EfficientNet based on FPGA", International Conference on Field-Programmable Technology (FPT), 2021. [link]
  2. Jingbo Gao, Wenbo Yin, Wai-Shing Luk, Lingli Wang, "Scalable multi-session TCP offload engine for latency-sensitive applications", China Semiconductor Technology International Conference (CSTIC), 2020. [link]

Honors & Awards